1. Field of the Invention
This invention relates to integrated circuits, and particularly to selective silicide formation using an electrochemical displacement reaction in the absence of an externally applied current or potential.
2. Description of Background
Integrated circuits often employ active devices known as transistors such as field effect transistors (FETs). A FET includes a silicon-based substrate comprising a pair of impurity regions, i.e., source and drain junctions, spaced apart by a channel region. A gate conductor is dielectrically spaced above the channel region of the silicon-based substrate. The junctions can comprise dopants which are opposite in type to the dopants residing within the channel region interposed between the junctions. The gate conductor can comprise a doped semiconductive material such as polycrystalline silicon (“polysilicon”). The gate conductor can serve as a mask for the channel region during the implantation of dopants into the adjacent source and drain junctions. An interlevel dielectric can be disposed across the transistors of an integrated circuit to isolate the gate areas and the junctions. Ohmic contacts can be formed through the interlevel dielectric down to the gate areas and/or junctions to couple them to overlying interconnect lines.
To reduce the contact resistances at the interfaces of the gate and the source and drain junctions, metal silicide structures can be formed between the ohmic contacts and the gate/junctions. FIGS. 1-4 illustrate a current process for forming such metal silicide structures. In FIG. 1, a FET is depicted that includes a portion of a silicon-based substrate 10 isolated from other regions of the substrate by shallow trench isolation structures 20 comprising a dielectric. A polysilicon gate 30 is spaced above the substrate 10 by a gate dielectric (not shown). Dielectric spacers 40 are formed upon the sidewalls of the gate 30. Source/drain junctions 50 are disposed in the substrate 10 on opposite sides of the gate 30/spacers 40. As shown in FIG. 2, the formation of the metal silicide first involves using a nonselective, vacuum deposition method, e.g., sputtering, to blanket deposit a metal film 60 across the semiconductor topography from FIG. 1. As shown in FIG. 3, the deposited metal film 60 can then be annealed to react the metal only in regions where silicon atoms are present while regions bearing no active silicon, e.g. dielectric regions, remain unreacted. In this manner, self-aligned metal silicide structures 70 can be formed exclusively upon the source/drain junctions 50 and the polysilicon gate 30. As illustrated in FIG. 4, the excess, unreacted metal 60 can be removed using a wet chemical etch. Removing the metal in this manner can undesirably damage the silicide if the wet etch process is not carefully controlled.